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rt9911 1 ds9911-05 april 2011 www.richtek.com 6 channel dc/dc converters general description the rt9911 is a complete power-supply solution for digital still cameras and other hand-held devices. it integrates one selectable boost/buck dc/dc converter, one high efficiency step-down dc/dc converter, one high efficiency main step-up converter, one pwm converter for ccd positive voltage, one inverter for ccd negative voltage and one white led driver f or lcd backlight. the rt9911 is targeted for applications that use either two or three primary cells or a single lithium-ion battery. rt9911 is available in vqfn-40l 6x6. each dc-dc converter has independent shutdown input. features z z z z z 1.6v to 5.5v battery input voltage range z z z z z synchronous boost/buck selectable dc/dc converter ` internal switches ` up to 95% efficiency z z z z z syn-buck dc/dc converters ` 0.8v to 5.5v adjustable output voltage ` up to 95% efficiency ` 100% (max) duty cycle ` internal switches z z z z z main boost dc/dc converter ` adjustable output voltage ` up to 97% efficiency z z z z z pwm converter for ccd positive voltage z z z z z inverter for ccd negative voltage z z z z z white led driver for lcd panel backlight z z z z z up to 1.4mhz adjustable switching frequency z z z z z 1 a supply current in shutdown mode z z z z z external compensation network for all converters z z z z z independent enable pin to shutdown each channel. z z z z z 40-lead vqfn package z z z z z rohs compliant and 100% lead (pb)-free applications z digital still camera z pda z protable device ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. pin configurations (top view) vqfn-40l 6x6 gnd ok2 rt vref vddm gnd fb1 comp1 pgnd1 lx1 lx2 pgnd2 fb3 comp3 cs3 drn3 drp3 vfb6 cfb6 comp6 comp2 pvdd2 en6 en5 en4 en3 en2 en1 fb2 select ext6 pvdd3 pvdd1 comp5 fb5 ext5 pvdd5 comp4 ext4 fb4 30 29 28 27 26 25 24 23 22 21 31 32 33 34 35 36 37 38 39 40 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 gnd 41 rt9911 package type qv : vqfn-40l 6x6 (v-type) lead plating system p : pb free g : green (halogen free and pb free)
rt9911 2 ds9911-05 april 2011 www.richtek.com typical application circuit figure 1. application circuit for 2-cells battery supply note : z bottom pad is gnd pad, can be short to pin 6 (gnd). z please remove q2 when use async boost and remove d5 when use sync boost. pvdd1 fb2 ok2 fb1 lx2 pvdd2 lx1 drn3 gnd gnd cs3 vref pvdd5 fb4 ext4 9 11 10 7 26 2 30 25 19 23 22 20 33 31 4 13 14 18 5 rt9911 pgnd1 10f v bat 2.2m 10f v bat 10f 1m 10fx2 125k 4.7f 10f v bat fb5 ext5 ext6 vfb6 cfb6 1f vddm select v bat 100pf 470k 150k 510k 300k 240k 10f v core 1.8v 300ma 10f v bat 10fx2 10fx2 10fx4 470k vs 3.3v drp3 fb3 90.9k motor 5v 500ma pvdd3 28 24 en1 en1 en3 en4 en5 en6 en1 en2 en3 en4 en5 en6 comp1 comp2 comp3 comp4 comp5 comp6 rt vs 3.3v ccd 12v 20ma ccd -8v/40ma vs 3.3v i/o 3.3v 500ma 83227161221 40 39 38 37 36 35 6 3 1 15 17 34 29 pgnd2 c1 to c2 c7 c9 c11 c12 to c13 c15 to c18 c19 c20 c21 c24 c26 to c27 4.7f c28 c29 c30 c31 to c36 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 10 r14 r15 to r21 l1 l4 l5 l6 l2 l3 ss0520 ss0520 ss0520 d1 d2 d3 q1 q3 q4 q5 q6 4.7h 10fx4 c3 to c6 0.1f c8 4.7h 100pf c10 4.7h 100pf c14 4.7h 100pf c22 205k 3.3h 100pf c25 4.7h 300k d4 3.3v 1f c23 q2 d5 d6 d7 d8 bottom pad 1.8v to 3.2v d9 1m 20k r22
rt9911 3 ds9911-05 april 2011 www.richtek.com figure 2. application circuit for li-ion battery supply note : z bottom pad is gnd pad, can be short to pin 6 (gnd). z please remove q2 when use async boost and remove d5 when use sync boost. z output voltage setting ch1: 0.8vx(1+r1/r2) ex: i/o 3.3v = 0.8x(1+470k/150k) ch2: 0.8vx(1+r4/r5) ex: ddr 2.5v = 0.8x(1+470k/226k) ch3: 0.8vx(1+r8/r9) ex: motor 5v = 0.8x(1+470k/90.9k) ch4: 1.0vx(1+r10/r11) ex: ccd 12v = 1.0x(1+2.2m/205k) ch5: -1.0vx(r13/r14) ex: ccd -8v = -1.0x(1m/125k) pvdd1 fb2 ok2 fb1 lx2 lx1 drn3 gnd gnd cs3 vref pvdd5 fb4 ext4 9 11 10 7 26 2 30 25 19 23 22 20 33 4 13 14 18 5 rt9911 pgnd1 10f v bat 2.2m 10f v bat 10f 1m 10f 125k 4.7f 10f v bat fb5 ext5 ext6 vfb6 cfb6 1f vddm select v bat 100pf 470k 150k 510k 470k 226k 10fx2 2.5v v bat 10fx2 10fx2 10fx4 470k drp3 fb3 90.9k motor 5v 500ma pvdd3 28 24 en1 en1 en3 en4 en5 en6 en1 en2 en3 en4 en5 en6 comp1 comp2 comp3 comp4 comp5 comp6 rt v bat ccd 12v 20ma ccd -8v 40ma 83227161221 40 39 38 37 36 35 6 3 1 15 17 34 29 pgnd2 c1 to c2 c7 c10 to c11 c15 to c16 c18 to c21 c22 c23 c24 c26 c28 4.7f c29 c30 c31 c32 to c37 r3 r1 r2 r4 r5 r8 r9 r10 r11 r12 r13 r14 r15 10 r16 r17 to r23 l1 l4 l5 l6 l2 l3 ss0520 ss0520 ss0520 d1 d2 d3 q1 q2 q3 q4 q5 q6 4.7h 100pf c25 205k 3.3h 100pf c27 4.7h 300k d4 4.7h 10fx4 c3 to c6 i/o 3.3v 500ma pvdd2 31 10fx2 v bat c8 to c9 4.7uh 100pf c12 4.7h 10pf c17 c13 ddr 2.5v 250ma d5 d6 d7 d8 bottom pad 3.4v to 4.2v 1m r24 20k 0.1f
rt9911 4 ds9911-05 april 2011 www.richtek.com + - rt vddm gnd + - vddm 1.0v vref + - 0.8v fb1 comp1 pgnd1 lx1 pvdd1 com p5 fb5 + - ext5 pv d d 5 + - 1.0v fb4 comp4 pin no. pin name pin function i/o internal state at shut down i/o configuration 1 gnd analog ground pin -- -- 2 ok2 external switch control. out high impedance 3 rt frequency setting pin. frequency is 500khz if rt pin not connected. out pull low 5 vddm device input power pin in -- 6 gnd analog ground pin -- -- 4 vref 1.0v reference pin out high impedance 7 fb1 feedback input pin of ch1. i n high impedance 8 comp1 feedback compensation pin of ch1. out pull low 9 pgnd1 power ground pin of ch1. -- -- 10 lx1 switch node of ch1. out high impedance 11 pv d d 1 power input pin of ch 1. in -- 12 comp5 feedback compensation pin of ch5. out pull low 13 fb5 feedback input pin of ch5. i n high impedance 14 ext5 externa l powe r switch of ch5. out pull hig h 15 pvdd5 power input pin of ch 4, ch 5 and ch6. in -- 16 comp4 feedback compensation pin of ch4. out pull low 17 fb4 feedback input pin of ch4. i n high impedance ok 2 gnd functional pin description to be continued
rt9911 5 ds9911-05 april 2011 www.richtek.com ext4 pvdd5 ext6 pvdd5 50ua vfb6 + - 1.0v drn3 pvdd3 cs3 vddm drp3 pvdd3 + - 0.2v cf b6 comp6 pin no. pin name pin function i/o internal state at shut down i/o configuration 18 ext4 external power switch of ch4. out pull low 19 ext6 external power switch of ch6. out pull low 20 pvdd3 power input pin of ch3. in -- 24 drp3 external pmos switch pin for ch3. out pull high 21 comp6 feedback compensation pin of ch6. out pull low 22 cfb6 current feedback input pin for ch6. in high impedance 23 vfb6 voltage feedback input pin for ch6. in high impedance 25 drn3 external nmos switch pin for ch3. out pull low 26 cs3 current sense input pin for ch3 in high impedance to be continued
rt9911 6 ds9911-05 april 2011 www.richtek.com pgnd2 lx2 pvdd2 + - 0.8v fb2 comp2 select 2ua vddm en1 2ua vddm en2 2ua vddm pin no. pin name pin function i/o internal state at shut down i/o configuration 27 comp3 feedback compensation pin of ch3 out pull low 28 fb3 feedback input pin of ch3. in high impedance 29 pgnd2 power ground pin of ch2 -- -- 30 lx2 switch node of ch2 out high impedance 31 pvdd2 power input pin of ch2. in -- 32 comp2 feedback compensation pin of ch2. out pull low 33 fb2 feedback input pin of ch2. in high impedance 34 select ch1 boost/buck selection pin. logic state can?t be changed during operation. in pull low 35 en1 enable input pin of ch1. in pull low 36 en2 enable input pin of ch2. in pull low + - 0.8v fb3 comp3 to be continued
rt9911 7 ds9911-05 april 2011 www.richtek.com en3 2ua vddm en4 2ua vddm en5 2ua vddm en6 2ua vddm pin no. pin name pin function i/o internal state at shut down i/o configuration 37 en3 enable input pin of ch3. in pull low 38 en4 enable input pin of ch4. in pull low 39 en5 enable input pin of ch5. in pull low 40 en6 enable input pin of ch6. in pull low exposed pad (41) gnd the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. -- -- --
rt9911 8 ds9911-05 april 2011 www.richtek.com function block diagram ch1 c-mode step-up or step-down + - 0.8v ref ch2 c-mode step-down + - 0.8v ref ch3 c-mode step-up + - 0.8v ref ch4 v-mode step-up pwm pvdd5 + - 1.0v ref ch5 inverter + - 1.0v ref ch6 wled pvdd5 + - 1.0v ref 50ua + - 0.2v ref switch controller oscillator thermal shutdown ok2 vref vfb6 cfb6 comp6 ext6 comp5 fb5 ext5 pvdd5 comp4 ext4 fb4 en6 en5 en4 vddm gnd fb1 comp1 pgnd1 lx1 lx2 pgnd2 fb3 comp3 cs3 drn3 drp3 pvdd3 pvdd1 comp2 pvdd2 en2 en1 fb2 select en3 pvdd3 rt
rt9911 9 ds9911-05 april 2011 www.richtek.com absolute maximum ratings (note 1) z supply voltage, v ddm ----------------------------------------------------------------------------------------- ? 0.3v to 7v z power switch ---------------------------------------------------------------------------------------------------- ? 0.3v to (v dd + 0.3v) z the other pins -------------------------------------------------------------------------------------------------- ? 0.3v to 7v z power dissipation, p d @ t a = 25 c vqfn ? 40l 6x6 -------------------------------------------------------------------------------------------------- 2.778w z package thermal resistance (note 2) vqfn-40l 6x6, ja --------------------------------------------------------------------------------------------- 36 c/w z junction temperature ------------------------------------------------------------------------------------------ 150 c z lead temperature (soldering, 10 sec.) -------------------------------------------------------------------- 260 c z storage temperature range --------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body mode) ----------------------------------------------------------------------------------- 2kv mm (ma chine mode) ------------------------------------------------------------------------------------------- 200v recommended operating conditions (note 4) z dimming control frequency range, ch6 ---------------------------------------------------------------- 300hz to 900hz z supply voltage, v ddm ----------------------------------------------------------------------------------------- 2.4v to 5.5v z junction temperature range --------------------------------------------------------------------------------- ? 40 c to 125 c z operation temperature range ------------------------------------------------------------------------------- ? 40 c to 85 c electrical characteristics to be continued parameter symbol test conditions min typ max unit supply voltage vddm minimum startup voltage v st (note 5) -- -- 1.6 v vddm operating voltage v ddm vddm pin voltage 2.4 -- 5.5 v vddm over voltage protection 5.9 6.5 -- v supply current shutdown supply current into vddm i off en1 = en2 = en3 = en4 = en5 = en6 = 0v -- 1 10 a ch1 (sync-boost or syn-buck) supply current into vddm i q1 v ddm = 3.3v, non-switching -- -- 430 a ch2 (sync-buck) supply current into vddm i q2 v ddm = 3.3v, non-switching -- -- 350 a ch3 (sync-boost) supply current into vddm i q3 v ddm = 3.3v, non-switching -- -- 350 a ch4 (asyn-boost) supply current into vddm i q4 v ddm = 3.3v, non-switching -- -- 300 a ch5 (asyn-inverter) supply current into vddm i q5 v ddm = 3.3v, non-switching -- -- 300 a ch6 (asyn-boost) supply current into vddm i q6 v ddm = 3.3v, non-switching -- -- 350 a (v ddm = 3.3v, t a = 25 c, unless otherwise specified)
rt9911 10 ds9911-05 april 2011 www.richtek.com parameter symbol test conditions min typ max unit oscillator operation frequency f osc rt open 450 550 650 khz ch1 maximum duty cycle (boost) d max1 select = 3.3v, v fb1 = 0.7v 80 85 90 % ch1 maximum duty cycle (buck) d max1 select = 0v, v fb1 = 0.7v 100 -- -- % ch2 maximum duty cycle d max2 v fb2 = 0.7v 100 -- -- % ch3 maximum duty cycle d max3 v fb3 = 0.7v 75 80 90 % ch4 maximum duty cycle d max4 v fb4 = 0.9v ch5 maximum duty cycle d max5 v fb5 = 0.1v ch6 maximum duty cycle d max6 v cfb6 = 0.18v, v fb6 = 0.9v 90 94 98 % feedback regulation voltage feedback regulation voltage @ fb1, fb2, fb3 v fb1, 2,3 0.788 0.8 0.812 v feedback regulation voltage @fb4 v fb4 0.98 1 1.02 v feedback regulation voltage @ fb5 v fb5 ? 15 -- +15 mv feedback regulation voltage @ vfb6 v vfb6 -- 1 -- v feedback regulation voltage @ cfb6 v cfb6 0.18 0.2 0.22 v reference vref output voltage v ref 0.984 1 1.016 v vref load regulation 0 a < i ref < 100 a -- -- 10 mv error amplifier gm (ch1, ch2, ch3, ch4, ch5, ch6) -- 0.2 -- ms compensation source current (ch1, ch2, ch3, ch4, ch5, ch6) -- 22 -- a compensation sink current (ch1, ch2, ch3, ch4, ch5, ch6) -- 22 -- a power switch r ds(on)p1 p-mosfet, pv dd1 = 3.3v -- 200 300 m ch1 on resistance of mosfet r ds(on)n1 n-mosfet, pv dd1 = 3.3v -- 200 300 m ch1 switch current limitation (buck ) select=0 1.3 2 4 a ch1 switch current limitation (boost) select=1 2 2.5 4 a r ds(on)p2 p-mosfet, pv dd2 = 3.3v -- 300 450 m ch2 on resistance of mosfet r ds(on)n2 n-mosfet, pv dd2 = 3.3v -- 300 450 m ch2 switch current limitation 1.3 2 4 a r ds(on)np3 p-mosfet, pv dd3 = 3.3v -- 6 15 ch3 on resistance of drn3 r ds(on)nn3 n-mosfet, pv dd3 = 3.3v -- 6 15 r ds(on)pp3 p-mosfet, pv dd3 = 3.3v -- 6 15 ch3 on resistance of drp3 r ds(on)pn3 n-mosfet, pv dd3 = 3.3v -- 6 15 r ds(on)p4 p-mosfet, pv dd3 = 3.3v -- 6 15 ch4 on resistance of mosfet r ds(on)n4 n-mosfet, pv dd3 = 3.3v -- 6 15 to be continued
rt9911 11 ds9911-05 april 2011 www.richtek.com parameter symbol test conditions min typ max unit power switch r ds(on)p5 p-mosfet, pv dd5 = 3.3v -- 6 15 ch5 on resistance of mosfet r ds(on)n5 n-mosfet, pv dd5 = 3.3v -- 6 15 r ds(on)p6 p-mosfet, pv dd5 = 3.3v -- 6 15 ch6 on resistance of mosfet r ds(on)n6 n-mosfet, pv dd5 = 3.3v -- 6 15 switch controller ok2 pin sink current ok2 = 1v 90 -- -- a external current setting (ch3) cs3 sourcing current i cs3 5 10 15 a vfb6 sink current i vfb6 40 50 60 a protection under voltage protection threshold voltage @ fb1, fb2 select = 0v 0.3 0.4 0.5 v over voltage protection @ fb1, fb2 select = 0v -- 1 -- v control en1, en2, en3, en4, en5, en6 input high level threshold v ddm = 3.3v -- -- 1.3 v en1, en2, en3, en4, en5, en6 input low level threshold v ddm = 3.3v 0.4 -- -- v en1, en2, en3, en4, en5, en6 sink current v ddm = 3.3v -- 2 6 a select pin input high level threshold -- -- 1.3 v select pin input low level threshold 0.4 -- -- v select pin sink current i select -- 2 6 a thermal protection thermal shutdown t sd 125 180 -- c thermal shutdown hysteresis t sd -- 20 -- c note 1. stresses listed as the above ? absolute maximum ratings ? may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in the natural convection at t a = 25 c on a low effective thermal conductivity test board of jedec 51-3 thermal measurement standard. note 3. devices are esd sensitive. handling precaution recommended. note 4. the device is not guaranteed to function outside its operating conditions. note 5. a schottky retifier connected from lx1 to pvdd1 is required for low-voltage startup, refer to figure 1.
rt9911 12 ds9911-05 april 2011 www.richtek.com typical operating characteristics ch1 buck load transient response time (1ms/div) v out (100mv/div) i out (200ma/div) v in = 4.2v, v out = 3.3v ch1 boost load transient response time (1ms/div) v out (100mv/div) i out (100ma/div) v in = 3.0v, v out = 3.3v v in = 1.8v, v out = 3.3v, i out = 100ma ch1 boost lx1 and output voltage ripple lx1 (2v/div) time (1 s/div) v out (10mv/div) v in = 4.2v, v out = 3.3v, i out = 100ma lx1 (2v/div) time (1 s/div) v out (10mv/div) ch1 buck lx1 and output voltage ripple ch1 buck efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 10 100 1000 output current (ma) efficiency (%) v in = 3.0v = 3.4v = 3.8v = 4.5v ch1 buck v out = 2.5v ch1 boost efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 10 100 1000 output current (ma) efficiency (%) v in = 3.2v = 2.5v = 2.0v = 1.5v ch1 boost v out = 3.3v
rt9911 13 ds9911-05 april 2011 www.richtek.com v in = 3.3v, v out = 1.8v, i out = 300ma ch2 lx2 and output voltage ripple lx2 (2v/div) time (1 s/div) v out (10mv/div) v in = 4.2v, v out = 2.5v, i out = 400ma ch2 lx2 and output voltage ripple lx2 (2v/div) time (1 s/div) v out (10mv/div) ch2 buck efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 10 100 1000 output current (ma) efficiency (%) v in = 2.5v = 3.0v = 3.8v = 4.5v v out = 1.8v ch1 buck output voltage vs. output current 3.365 3.366 3.367 3.368 3.369 3.370 3.371 3.372 3.373 3.374 3.375 0 100 200 300 400 500 600 700 800 900 loading current (ma) output voltages (v) v in = 3.7v, v out = 3.3v ch1 boost output voltage vs. output current 3.320 3.321 3.322 3.323 3.324 3.325 3.326 3.327 3.328 3.329 3.330 0 100 200 300 400 500 600 700 800 900 output current (ma) output voltages (v) v in = 2.4v, v out = 3.3v ch1 boost output voltage vs. v ddm voltage 3.20 3.21 3.22 3.23 3.24 3.25 3.26 3.27 3.28 3.29 3.30 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6 v ddm voltage (v) output voltage (v) v in = 2.5v, v out = 3.3v, i out = 250ma
rt9911 14 ds9911-05 april 2011 www.richtek.com ch2 load transient response time (1ms/div) v out (20mv/div) i out (200ma/div) v in = 4.2v, v out = 2.5v ch2 load transient response time (1ms/div) v out (20mv/div) i out (200ma/div) v in = 3.0v, v out = 2.5v ch2 load transient response time (1ms/div) v out (20mv/div) i out (100ma/div) v in = 3.3v, v out = 1.8v ch2 output voltage vs. v ddm voltage 1.74 1.75 1.76 1.77 1.78 1.79 1.80 1.81 1.82 1.83 1.84 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2 5.6 v ddm voltage (v) output voltage (v) v in = 3.3v, v out = 1.8v, i out = 250ma ch2 buck output voltage vs. output current 1.805 1.806 1.807 1.808 1.809 1.810 1.811 1.812 1.813 1.814 1.815 0 100 200 300 400 500 600 700 800 900 100 0 output current (ma) output voltages (v) v in = 3.7v, v out = 1.8v 1000 ch2 buck output voltage vs. output current 3.270 3.280 3.290 3.300 3.310 3.320 3.330 3.340 3.350 3.360 3.370 0 100 200 300 400 500 600 700 800 900 100 0 output current (ma) output voltages (v) v in = 3.7v, v out = 3.3v 1000
rt9911 15 ds9911-05 april 2011 www.richtek.com v in = 1.8v, v out = 5v, i out = 350ma ch3 lx3 and output voltage ripple lx3 (2v/div) time (1 s/div) v out (20mv/div) v in = 1.8v, v out = 3.3v, i out = 400ma ch3 lx3 and output voltage ripple lx3 (2v/div) time (1 s/div) v out (20mv/div) time (1ms/div) v out (100mv/div) i out (200ma/div) v in = 3.0v, v out = 3.3v ch3 load transient response ch3 boost efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 10 100 1000 output current (ma) efficiency (%) v in = 3.2v = 2.5v = 2.0v = 1.5v v out = 3.3v ch3 boost efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 10 100 1000 output current (ma) efficiency (%) v in = 4.5v = 3.8v = 3.2v = 2.5v = 2.0v = 1.5v v out = 5v ch3 boost efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 10 100 1000 output current (ma) efficiency (%) v out = 3.3v v in = 3.0v async = 2.4v async = 1.5v async = 3.0v sync = 2.4v sync = 1.5v sync
rt9911 16 ds9911-05 april 2011 www.richtek.com ch4 load transient response time (1ms/div) v out (100mv/div) i out (20ma/div) v in = 1.8v, v out = 12v ch4 boost efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 1 10 100 output current (ma) efficiency (%) v in = 4.5v = 3.8v = 3.2v = 2.5v = 2.0v = 1.5v v out = 12v ch3 boost output voltage vs. v ddm voltage 3.20 3.21 3.22 3.23 3.24 3.25 3.26 3.27 3.28 3.29 3.30 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6 v ddm voltage (v) output voltage (v) v in = 2.5v, v out = 3.3v, i out = 250ma ch3 boost output voltage vs. v ddm voltage 4.98 4.99 5.00 5.01 5.02 5.03 5.04 5.05 5.06 5.07 5.08 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2 5.6 v ddm voltage (v) output voltage (v) v in = 2.5v, v out = 5.0v, i out = 250ma ch3 boost output voltage vs. output current 4.975 4.980 4.985 4.990 4.995 5.000 5.005 5.010 5.015 5.020 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 output current (a) output voltage (v) v in = 3.7v, v out = 5v v in = 1.8v, v out = 12v, i out = 30ma ch4 lx4 and output voltage ripple lx4 (5v/div) time (1 s/div) v out (20mv/div)
rt9911 17 ds9911-05 april 2011 www.richtek.com v in = 1.8v, v out = -8v, i out = 50ma ch5 lx5 and output voltage ripple lx5 (5v/div) time (1 s/div) v out (20mv/div) ch5 inverting efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 110100 output current (ma) efficiency (%) v in = 1.5v = 2.0v = 2.5v = 4.5v = 3.2v = 3.8v v out = -8v ch4 output voltage vs. v ddm voltage 15.32 15.33 15.34 15.35 15.36 15.37 15.38 15.39 15.40 15.41 15.42 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2 5.6 v ddm voltage (v) output voltage (v) v in = 2.5v, pvdd5 = 3.3v, i out = 30ma ch4 output voltage vs. v ddm voltage 11.78 11.79 11.80 11.81 11.82 11.83 11.84 11.85 11.86 11.87 11.88 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2 5.6 v ddm voltage (v) output voltage (v) v in = 2.5v, pvdd5 = 3.3v, i out = 30ma ch5 load transient response time (1ms/div) v out (100mv/div) i out (20ma/div) v in = 1.8v, v out = -8v ch4 boost output voltage vs. output current 15.730 15.735 15.740 15.745 15.750 15.755 15.760 15.765 15.770 15.775 15.780 0 102030405060708090100 output current (ma) output voltages (v) v in = 3.7v, v out = 15.5v
rt9911 18 ds9911-05 april 2011 www.richtek.com v in = 1.8v, v out = 3 x wled, i out = 20ma ch6 lx6 and output voltage ripple lx6 (5v/div) time (1 s/div) v out (20mv/div) ch6 efficiency vs. input voltage 0 10 20 30 40 50 60 70 80 90 100 1.522.533.544.55 input voltage (v) efficiency (%) i out = 20ma ch5 output voltage vs. output current -8.152 -8.151 -8.150 -8.149 -8.148 -8.147 -8.146 -8.145 -8.144 -8.143 -8.142 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 loading current (ma) output voltages (v) v in = 3.7v, v out = -8v ch7 load transient response time (1ms/div) v out (10mv/div) i out (200ma/div) v in = 2.5v, v out = 1.8v ch5 output voltage vs. v ddm voltage -8.12 -8.11 -8.10 -8.09 -8.08 -8.07 -8.06 -8.05 -8.04 -8.03 -8.02 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2 5.6 v ddm voltage (v) output voltage (v) v in = 3.0v, pvdd5 = 3.3v, i out = 30ma ch5 output voltage vs. v ddm voltage -6.12 -6.11 -6.10 -6.09 -6.08 -6.07 -6.06 -6.05 -6.04 -6.03 -6.02 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2 5.6 v ddm voltage (v) output voltage (v) v in = 3.0v, pvdd5 = 3.3v, i out = 30ma
rt9911 19 ds9911-05 april 2011 www.richtek.com feedback voltage vs. temperature 0.72 0.76 0.80 0.84 0.88 0.92 0.96 1.00 1.04 -40-20 0 20406080100 temperature feedback voltage (v) v fb4 , v fb6 v fb1 , v fb2 , v fb3 ( c) ch4 and ch5 power sequence time (2ms/div) en4/en5 (2v/div) v out _ch4 (5v/div) v out _ch5 (5v/div) start up, v in = 2.5v ch1 and ch2 power sequence time (1ms/div) start up, v in = 2.5v en1/en2 (2v/div) v out _ch1 (2v/div) v out _ch2 (2v/div)
rt9911 20 ds9911-05 april 2011 www.richtek.com applications information the rt9911 incl udes the following six dc/dc converter channels to build a multiple-output power-supply system. ch1 : selectable step-up or step-down synchronous current mode dc/dc converter with internal power mosfets. ch2 : step-down synchronous current mode dc/dc converter with internal power mosfets. ch 3 : step-up asynchronous c urrent mode dc/dc controller to drive external power mosfets. ch4 : step-up asynchronous voltage mode dc/dc controller. ch5 : inverting dc/dc voltage mode controller. ch6 : dc/dc voltage mode controller for wled as well as conventional boost application; provides open led ovp protection. ch1 : selectable step-up or step-down converter ch1 is selectable as step-up (select pin = logic high) or step-down (select pin = logic low). step-up : with internal mosfets and synchronous rectifier, the efficiency is up to 95%. the converter always operates at fixed frequency pwm mode and ccm (continuous current mode). step-down : with internal mosfets and synchronous rectifier, the efficiency is up to 95%. the converter always operates at fixed frequency pwm mode and ccm. while the input voltage is close to output voltage, the converter enters low dropout mode. duty could be as long as 100% to extend battery life. see figure 3(a) for detailed functional block. ch2 : step-down dc/dc converter with internal mosfets and synchronous rectifier, the efficiency is up to 95%. the converter always operates at fixed frequency pwm mode and ccm. while the input voltage is close to output voltage, the converter enters low dropout mode. duty could be as long as 100% to extend battery life. see figure 3(b) for detailed functional block. ch3 : step-up dc/dc controller with externa l mosfets and a synchronous rectifier, the efficiency is up to 97%. the c onverter always operates at fixed frequency pwm mode and ccm. the threshold of current limit is estimated by r ds(on) of external nmos. see protections for detailed information and detailed functional block in figure 3(c). ch4, ch6 : step-up dc/dc controller ch4 and ch6 are fixed frequency voltage mode pwm controllers. ext4 and ext6 pins are designed to drive external nmos switch. ch6 is optimized for wled application. cfb6 is current-sensing feedback, and vfb6 provides over voltage protection (wled open circuit). see protections for detailed information and detailed functional block in figure 3(d for ch4 and e for ch6). ch5 : inverting controller ch5 is a voltage mode, fixed frequency pwm controller to generate negative output voltage. ext5 is designed to drive external pmos switch. to turn off pmos completely, please note that pvdd5 sh ould not be lower than the source voltage of pmos. see figure 3(f) for detailed functional block. reference voltage rt9911 provides a precise 1v reference voltage with souring capability 100 a. connect a 1 f ceramic capacitor from vref pin to gnd. reference voltage is enabled by connecting en5 to logic high.
rt9911 21 ds9911-05 april 2011 www.richtek.com current sense slope compensation logic driver fault protection pvdd1 lx1 pgnd1 osc 0.8v fb1 s r q comp1 select + - + - - current sense slope compensation logic driver fault protection pvdd2 lx2 pgnd2 osc 0.8v fb2 s r q comp2 + - + - - current sense slope compensation logic driver fault protection pvdd3 pgnd2 osc 0.8v fb3 s r q comp3 + - + - - drp3 drn3 cs3 triangle wave logic driver pvdd5 gnd osc 1.0v fb4 s r q comp4 + - + - ext4 diming control triangle wave logic driver fault protection pvdd5 gnd osc cfb6 s r q comp6 + - + - ext6 en6 0.2v + triangle wave logic driver pvdd5 gnd osc fb5 gnd s r q comp5 + - + - ext5 figure 3. detailed functional block for each channel figure 3(a) figure 3(c) figure 3(f) figure 3(e) figure 3(b) figure 3(d)
rt9911 22 ds9911-05 april 2011 www.richtek.com calculation method: td1 to td6 are precise value. tr1 to tr6 are approximation. units : t in second, c in farad, r in ohm c31 to c36 : compensation capacitor of ch1 to ch6. t1d = 0.7v x c31 / 2 a (ch1 boost) t1d = 0.7v x c31 / 2 a (ch1 buck) t2d = 0.35v x c32 / 2 a t3d = 0.7v x c33 / 2 a t4d = 0.35v x c34 / 2 a t5d = 0.85v x c35 / 2 a t6d = 0.85v x c36 / 2 a t1r = (0.5v x d1 + 0.48a x r ds(on)_n x c31 /1.25 a @ no load (boost) t1r = (0.33v x d1 + 0.2a x r ds(on)_p x c31 /1.25 a @ no load (buck) t2r = (0.33v x d2 + 0.2a x r ds(on)_p x c32 /1.25 a @ no load vddm (vs 3.3v) en1 to en6 vs 3.3v v core 1.8v motor 5v ccd 12v ccd - 8v wled t1d t1r t2d t2r t3d t3r t4d t4r t5d t5r t6d t6r v i/o 3.3v v bat figure 4. timing diagram t3r = (0.5v x d3 + 0.8a x r ds(on)_n x c33 /3.6 a @ no load t4r = (1.0v x d4) x c34 / 1 a @ no load t5r = (1.0v x d5) x c35 / 1 a @ 1ma min. load t6r = (0.25v x d6) x c36 / 2.6 a @ 4 wleds where d1 = 1 ? (v bat / v vs 3.3v ) (boost) d1 = v vs 3.3v / v bat (buck) d2 = v vcore 1.8v / v bat d3 = 1 ? (v bat / v motor 5v ) d4 = 1 ? (v bat / v ccd 12v ) d5 = |v ccd -8v | / ( v bat + |v ccd -8v |) d6 = 1 ? (v bat / v wled ) example : t1d = 0.7v x 1nf / 2 a = 350 s (boost) t1r = (0.5 x (1 ? 1.8/3.3) + 0.48 x 0.2) x 1nf / 1.25 a = 258 s note : z please refer to figure 1 for application information. z timing sequence should be controlled by en pins.
rt9911 23 ds9911-05 april 2011 www.richtek.com note : if r ds(on) x i inductor > 0.3v, then current limit happens. for example, if select nmos( aos3402), r ds(on) =110m (at v gs = 2.5v), then current limt happens if i inductor > 2.73a. protection type threshold (typical) refer to electrical spec protection methods reset method vddm over voltage protection vddm > 6.5v disable all channels restart if vddm < 6.5v ch1: boost current limit nmos current> 2.5a nmos latched off automatic reset at next clock cycle current limit pmos current > 2.0a pmos latched off and all channels shutdown vddm power reset under voltage protection fb1 < 0.4v nmos, pmos latch off and all channels shutdown vddm power reset ch1: buck over voltage protection fb1 > 1.0v nmos, pmos latch off and all channels shutdown vddm power reset current limit pmos current > 2.0a pmos latched off and all channels shutdown vddm power reset under voltage protection fb2 < 0.4v nmos, pmos latch off and all channels shutdown vddm power reset ch2 over voltage protection fb2 > 1.0v nmos, pmos latch off and all channels shutdown vddm power reset ch3 current limit cs3 > 0.3v, see below note nmos latched off automatic reset at next clock cycle ch6 over voltage protection vfb6 > 1.0v, see figure 8 nmos off vfb6 < 1.0v thermal thermal shutdown temperature > 180c all channels stop switching temperature < 160c table 1 figure 5. adjust frequency oscillator frequency v s. r rt 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 10 100 1000 r rt (k ? ) oscillator frequency (khz) 1 oscillator the internal oscillator synchronizes ch1 to ch6 with fixed operation frequency. the frequency could be set by connecting resistor between rt pin to gnd. se e figure 5 to adjust frequency. soft start with internal soft start mechanism, the soft start time of each channel is proportional to the compensation capacitor. refer to the soft start waveform in figure 4 for t ypical application. protection rt9911 provides versatile protection functions. protection type, threshold and protection methods are summarized in table 1.
rt9911 24 ds9911-05 april 2011 www.richtek.com rt9911 component selection for compensation : ch1 sync-boost (select pin = high logic) : ch1 sync-boost converter employs current-mode control to simplify the control loop compensation. there is a rhpz (right hand plane zero) appeared in the loop-gain frequency response when a boost converter operates with continuous inductor current (typically the case), we also call it works in ccm (continuous current mode). for stability, cross over frequency (f c ), unity gain frequency, must lower than this rhpz frequency. the fixed parameters for ch1 boost compensation are as follows : z transconductance (from fb to comp), gm = 200 s z current sense transresistance, r cs = 0.4v/a z feedback voltage, v fb = fb = 0.8v the input parameters for ch1 boost compensation are as follows: z r1, the voltage divider resistor in between v out and fb. z v in , input voltage. z v out , desired output voltage z i out(max.) , maximum output load z f osc , operating frequency z l, inductance z r esr , esr (equivalent series resistance) of c out (ceramic output capacitor) z t drp (%), transient droop. the results we will get for ch1 boost compensation are as follows: z r2, the voltage divider resistor in between fb and ground. z c f , fee dforward capacitor in parallel with r1. z r c , compensation resistor on comp pin. z c c , compensation capacitor in series with rc and connect to ground. z c p , connect in between comp pin and ground. (can be ignored if c p < 10pf). z c out , output capacitance. this compensation is based on ceramic output capacitor. ch3 pwm v ddm 10 a cs3 drn3 v bat lx3 i inductor figure 6. ch3 current limit setting figure 8. ch6 over voltage protection method (v wled > 50 a x r+1v, protection happens) figure 7 + - 1v ch6 pwm v bat wled ext6 vfb6 cfb6 50 a r + - 0.8v v out i out r esr c f c out r1 r2 r c c c c p fb comp gm
rt9911 25 ds9911-05 april 2011 www.richtek.com ch1 sync-buck (select pin = low logic) and ch2 sync-buck : ch1 sync-buck (select pin=low logic) and ch2 sync-buck are converters employ current-mode control to simplify the control loop compensation. th ere is no rhpz (right hand plan zero) in the buck topology but there is a high frequency pole f hp >= f osc / . the f c (cross over frequency) is chosen sufficient less than f hp . the fixed parameters for ch1 and ch2 buck compensation are as follows: z transconductance (from fb to comp), gm = 200 s z current sense transresistance, r cs = 0.3v/a z feedback voltage, v fb = fb = 0.8v the input parameters for ch1 and ch2 buck compensation are as follows: z r1, the voltage divider resistor in between v out and fb. the major steps for getting above results : 1. 2. find rhpz(right hand plan zero) location. 3. set f c (cross over frequency) sufficiently below rhpz. for example : f c = rhpz/6 4. get 5. select rc based on the allowed transient droop. , where di = transient step, dv fb = t drp (%) x v fb 6. get 7. find ffz, zero and ffp, pole ratio of voltage divider with c f . 8. get c f by placing ffp on f c and ffz therefore on . 9. evaluate c p . c p is for canceling the zero from c out (ceramic output capacitor). example : set r1 = 470k , v in = 1.8v, v out = 3.3v, v fb = 0.8v, i out(max.) = 0.5a, f osc = 500khz, l = 4.7 h, r esr = 5m , and half-load transient droop is 5%. results: 1. 2. 3. 4. half-load transient means load from 0.25a to 0.5a transient. so, di=0.5 ? 0.25=0.25a dv fb = t drp (%) x v fb = 5% x 0.8 = 0.04v. thus, 5. 6. 7. 8. choose c f = 150pf 9. which is less than 10pf. so, it can be ignored. ? ? ? ? ? ? ? ? = ) v - (v v x r1 r2 fb out fb out in out(max.) out load 2 load v v - 1 cycle duty d , i v r where , l 2 d) - (1 x r ) rhpz(boost = = = = d) - (1 x v v x f 2 gm x r r c out fb c cs load c ? ? ? ? ? ? = cs c fb 1r r = di x ( ) x (1- d) gm x dv load c c out r c x r c = fb out v v ffp ffz ratio = = ratio f ffz where , r1 x ffz x x 2 1 c c f = = ratio f c 10pf. c if ignore be can c . r r c c p p c esr out p < = = = = 150k 0.8 - 3.3 0.8 470k v - v v r1 r2 fb out fb 0.54 v v d) - (1 , 6.6 i v r where 66.3khz, l 2 d) - (1 r ) rhpz(boost out in out(max) out load 2 load = = = = = = 11khz 6 rhpz f c = = 6.8nf. choose 6.3nf. d) (1 x v v x f 2 gm r r c out fb c cs load c = ? ? ? ? ? ? ? = = ? ? ? ? ? ? ? ? = 23k dv x gm r x d) - (1 1 di r fb cs c . f 22 6 . 6 6.8n x 23k r c x r c load c c out = = = out fb ffp v3.3 ratio = = = = 4.1 ffz v 0.8 out esr p c 22 f x 0.005 c x r c = = = 4.8pf , r 23k 2.68khz 4.1 11k ratio f ff where 126pf, r1 ff 2 1 c c z z f = = = = =
rt9911 26 ds9911-05 april 2011 www.richtek.com z v in , input voltage. z v out , desired output voltage z i out(max.) , maximum output load z f osc , operating frequency z l, inductance z r esr , esr (equivalent series resistance) of c out (ceramic output capacitor) z t drp (%), transient droop. the results we will get for ch1 boost compensation are as follows: z r2, the voltage divider resistor in between fb and ground. z c f , feedforward capacitor in parallel with r1. z r c , compensation resistor on comp pin. z c c , compensation capacitor in series with r c and connect to ground z c p , connect in between comp pin and ground. (can be ignored if c p < 10pf) z c out , output capacitance. this compensation is based on ceramic output capacitor. f. 10 choose f. 10.8 6 . 3 3.9nf x 10k r c x r c load c c out = = = the major steps for getting above results : 1. 2. set fc (cross over frequency) sufficiently below f osc . for example : 3. 4. 5. 6. find ffz, zero and ffp, pole ratio of voltage divider with c f . 7. get c f by placing ffp on f c and ffz therefore on . 8. evaluate c p . c p is for canceling the zero from c out (ceramic output capacitor). example : set r1 = 470k , v in = 3v, v out = 1.8v, v fb = 0.8v, i out(max.) = 0.5a, f osc = 500khz, l = 4.7 h, r esr = 5m , and half-load transient droop is 5%. results : 1. 2. 3. choose 4.7nf. half-load transient means load from 0.25a to 0.5a transient. so, di = 0.5 ? 0.25=0.25a dv fb = t drp (%) x v fb = 5% x 0.8 = 0.04v. thus, 4. 5. 6. 7. choose c f = 22pf 8. which is less than 10pf. so, it can be ignored. fb out fb v - v v r1 r2 = cs c fb fb drp fb di x r r = , where di = transient step, gm x dv dv = t (%) x v load c c out r c x r c get = fb out v v ffz ffp ratio = = ratio f c 10pf. c if ignore be can c . r r x c c p p c esr out p < = = = = 376k 0.8 - 1.8 0.8 x 470k v - v v x r1 r2 fb out fb . 10k choose , 9.4k dv x gm r di r fb cs c = = 2.25 0.8 1.8 v v ffz ffp ratio fb out = = = = , 5pf 10k 0.005 x 10 r r x c c c esr out p = = = . ratio f ff where , r1 ff 2 1 c c z z f = = 22.2khz 2.25 50k ratio f ff where 15.2pf, r1 ff 2 1 c c z z f = = = = = 4 f f hp c = out fb c cs load c v v x f 2 gm x r r c = 40khz 4 f 4 f f osc hp c = = = = = = = 3.6 i v r where 4.25nf, v v x f 2 gm x r r c out(max.) out load out fb c cs load c
rt9911 27 ds9911-05 april 2011 www.richtek.com ch3 syn boost controller with external mosfet : ch3 boost controller driving external logic level mosfet employs current-mode control to simplify the control loop compensation. there is a rhpz (right hand plan zero) appeared in the loop-gain frequency response when a boost converter operates with continuous inductor current (typically the case), we also call it works in ccm (continuous current mode). for stability, cross over frequency (f c ), unity gain frequency, must lower than this rhpz frequency. the fixed parameters for ch3 boost compensation are as follows : z transconductance (from fb to comp), gm = 200 s z feedback voltage, v fb = fb = 0.8v the input parameters for boost compensation are as follows : z r ds(on) , the nmosfet r ds(on) , which is use to find transresistance, r cs . z r1, the voltage divider resistor in between v out and fb. z v in , input voltage. z v out , desired output voltage z i out(max.) , maximum output load z f osc , operating frequency z l, inductance z r esr , esr (equivalent series resistance) of c out (ceramic output capacitor) z t drp (%), transient droop. the results we will get for boost compensation are as follows : z r cs , the transresistance of current sense. z r2, the voltage divider resistor in between fb and ground. z c f , feedforward capacitor in parallel with r1. z r c , compensation resistor on comp pin. z c c , compensation capacitor in series with r c and connect to ground z c p , connect in between comp pin and ground. (can be ignored if c p < 10pf) z c out , output capacitance. this compensation is based on ceramic output capacitor. the major steps for getting above results : 1. r cs = 2 x r ds(on) the rest of the steps are the same as sync-boost. ch4 asyn-boost controller with external mosfet ch4 is an asyn-boost controller driving external logic level n type mosfet, which employs voltage mode control to regulate the output voltage. compensation depends on designing the loading range working in discontinuous or continuous inductor current mode. (dcm or ccm). asyn-boost in dcm : we call it dcm because inductor current falls to zero on each switch cycle. the benefit of designing in dcm is the simple loop compensation, which has no rhpz (right hand plan zero) and conjugate double pole in the frequency domain to worry about, but has a single load pole instead. however, the output ripple and efficiency are worse than in ccm (continuous inductor current). if the loading is around tens of ma, it is not bad to design in dcm with less impact on the output ripple and efficiency, but gain more easy to stabilize the control loop. the fixed parameters for ch4 asyn-boost in dcm compensation are as follows: z transconductance (from fb to comp), gm = 200us. z internal voltage ramp to decide duty cycle, v p = 1v. z feedback voltage, v fb = fb = 1v figure 9 + - 1v v out i out r esr c f c out r1 r2 r c c c c p fb comp gm
rt9911 28 ds9911-05 april 2011 www.richtek.com asyn-boost in ccm : we call it ccm because inductor current is always continuous in operation. the benefit of designing in ccm is lower v out and inductor current ripple and higher efficiency from the lower coil loss, but with the expense of larger inductor size and cost and the control loop comes with a rhpz (right hand plan zero) and a conjugate double pole in the frequency domain to worry about. the fixed parameters for ch4 asyn-boost in ccm compensation are as follows : z transconductance (from fb to comp), gm = 200 s z internal voltage ramp to decide duty cycle, v p = 1v z feedback voltage, v fb = fb = 1v the input parameters for ch4 asyn-boost in ccm compensation are as follows : z r1, the voltage divider resistor in between v out and fb. z v in , input voltage. z v out , desired output voltage z i out(max.) , maximum output load z i out(min.) , minimum output laod z f osc , operating frequency the input parameters for ch4 asyn-boost in dcm compensation are as follows : z r1, the voltage divider resistor in between v out and fb. z v in , input voltage. z v out , desired output voltage z i out(max.) , maximum output load z f osc , operating frequency z l, inductance z c out , output capacitance. this compensation is based on ceramic output capacitor. z r esr , esr (equivalent series resistance) of c out (ceramic output capacitor) the results we will get for ch4 asyn-boost in dcm compensation are as follows : z r2, the voltage divider resistor in between fb and ground. z c f , feedforward capacitor in parallel with r1. z r c , compensation resistor on comp pin. z c c , compensation capacitor in series with r c and connect to ground z c p , connect in between comp pin and ground. (can be ignored if c p < 10pf) the major steps for getting above results : 1. 2. select suitable inductor to ensure i out(min.) works in dcm, which is let inductor current falls to zero on each switch cycle. 3. set f c sufficient below f osc . for example: 4. 5. which is duty to v out transfer function. 6. 7. find ffz, zero and ffp, pole ratio of voltage divider with c f . 8. get c f by placing ffp on f c and ffz therefore on . 9. evaluate c p . c p is for canceling the zero from c out (ceramic output capacitor). fb out fb v - v v x r1 r2 = osc out(max.) in f x i x 2 d) - (1 x d x v l < lower or 10 f f osc c = . i v r , v v m where , c x r x 1) - (m x 2 1 - m x 2 f : pole load the find out(max.) out load in out out load lp = = = , 1 - m x 2 1 - m x d v x 2 g where , g x gm x v f f r get out dod dod p lp c c = = out in v v - 1 cycle duty d = = pole. load zero comp letting by r r x c c get c load out c = = fb out v v ffz ffp ratio = = ratio f c 10pf. c if ignore be can c . r r x c c p p c esr out p < = . ratio f ff where , r1 ff 2 1 c c z z f = =
rt9911 29 ds9911-05 april 2011 www.richtek.com ch5 asyn-inverter controller with external mosfet ch5 is an asyn-inverter controller driving external logic level p type mosfet, which employs voltage mode control to regulate the output voltage. compensation depends on designing the loading range working in discontinuous or continuous inductor current mode. (dcm or ccm). asyn-inverter in dcm : we call it dcm because inductor current falls to zero on each switch cycle. the benefit of designing in dcm is the simple loop compensation, which has no rhpz (right hand plan zero) and conjugate double pole in the frequency domain to worry about, but has a single load pole instead. however, the output ripple and efficiency are worse than in ccm (continuous inductor current). if the loading is around tens of ma, it is not bad to design in dcm with less impact on the output ripple and efficiency, but gain more easy to stabilize the control loop. the fixed parameters for ch5 asyn-inverter in dcm compensation are as follows: z transconductance (from fb to comp), gm = 200 s z internal voltage ramp to decide duty cycle, v p = 1v z feedback voltage, v fb = fb = 0v z reference voltage, v ref = 1v figure 10 z l, inductance z c out , output capacitance. this compensation is based on ceramic output capacitor. z r esr , esr (equivalent series resistance) of c out (ceramic output capacitor) the results we will get for ch4 asyn-boost in ccm compensation are as follows: z r2, the voltage divider resistor in between fb and ground. z c f , feedforward capacitor in parallel with r1. z r c , compensation resistor on comp pin. z c c , compensation capacitor in series with r c and connect to ground z c p , connect in between comp pin and ground. (can be ignored if c p < 10pf) the major steps for getting above results : 1. 2. select suitable inductor to ensure i out(min.) works in ccm, 3. find rhpz(right hand plan zero) location. 4. set f c (cross over frequency) sufficiently below rhpz. for example : 5. 6. which is duty to v out transfer function. 7. find which is the conjugate double pole from lc filter. 8. fb out fb v - v v x r1 r2 = osc out(min.) in f x i x 2 d) - (1 x d x v l > out in out(max) out load 2 load v v - 1 cycle duty d , i v r where , l 2 d) - (1 r ) rhpz(boost = = = = lower. r 6 rhpz f c o = . i v r , v v m where , c x r x 1) - (m x 2 1 - m x 2 f : pole load the find out(max.) out load in out out load lp = = = , d) - (1 v g where , g x gm x v f f r get 2 in doc doc p lp c c = = . v v - 1 cycle duty d out in = = , (lc) x 2 d - 1 f 2 cdp = pole. double the of one cancel to r x f x 2 1 c c cdp c = 9. find c f by placing its zero on f cdp to cancel another double pole. 10.evaluate c p . c p is for canceling the zero from c out (ceramic output capacitor). 10pf. c if ignore be can c . r r x c c p p c esr out p < = . r1 f 2 1 c cdp f = + - 0v v out i out r esr c f c out r1 r2 r c c c c p fb comp gm 4.7uf v ref = 1v 20k
rt9911 30 ds9911-05 april 2011 www.richtek.com the input parameters for ch5 asyn-inverter in dcm compensation are as follows : z r1, the voltage divider resistor in between v out and fb. z v in , input voltage. z v out , desired output voltage z i out(max.) , maximum output load z f osc , operating frequency z l, inductance z c out , output capacitance. this compensation is based on ceramic output capacitor. z r esr , esr (equivalent series resistance) of c out (ceramic output capacitor) the results we will get for ch5 asyn-inverter in dcm compensation are as follows : z r2, the voltage divider resistor in between fb and v ref . z c f , feedforward capacitor in parallel with r1. z r c , compensation resistor on comp pin. z c c , compensation capacitor in series with r c and connect to ground z c p , connect in between comp pin and ground. (can be ignored if c p < 10pf) asyn-inverter in ccm : we call it ccm because inductor current is always continuous in operation. the benefit of designing in ccm is lower v out and inductor current ripple and higher efficiency from the lower coil loss, but with the expense of larger inductor size and cost and the control loop comes with a rhpz (right hand plan zero) and a conjugate double pole in the frequency domain to worry about. the fixed parameters for ch5 asyn-inverter in ccm compensation are as follows : z transconductance (from fb to comp), gm = 200us z internal voltage ramp to decide duty cycle, v p = 1v z feedback voltage, v fb = fb = 0v z reference voltage, v ref = 1v the input parameters for ch5 asyn-inverter in ccm compensation are as follows : z r1, the voltage divider resistor in between v out and fb. z v in , input voltage. z v out , desired output voltage z i out(max.) , maximum output load the major steps for getting above results : 1. 2. select suitable inductor to ensure i out(min.) works in dcm, which is let inductor current falls to zero on each switch cycle. 3. set f c sufficient below f osc for example: 4. 5. which is duty to vout transfer function. 6. 7. find ffz, zero and ffp, pole ratio of voltage divider with c f . 8. get c f by placing ffp on f c and ffz therefore on . 9. evaluate c p . c p is for canceling the zero from c out (ceramic output capacitor). = = = = ? = 125k (-8) - 0 0 - 1 x 1m r2 then (-8)v v and 1m r1 if . v v v - v x r1 r2 out out fb fb ref osc out(max.) in f x i x 2 d) - (1 x v l < lower or 10 f f osc c = . i v r where , c x r x 2 2 f : pole load the find out(max.) out load out load lp = = , d v g where , g x gm x v f f r get out dod dod p lp c c = = . ) abs(v v ) abs(v cycle duty d out in out + = = pole. load zero comp letting by r r x c c get c load out c = = ref ref out v v ) abs(v ffz ffp ratio + = = ratio f c 10pf. c if ignore be can c . r r x c c p p c esr out p < = . ratio f ff where , r1 ff 2 1 c c z z f = =
rt9911 31 ds9911-05 april 2011 www.richtek.com z i out(min.) , minimum output laod z f osc , operating frequency z l, inductance z c out , output capacitance. this compensation is based on ceramic output capacitor. z r esr , esr (equivalent series resistance) of c out (ceramic output capacitor) the results we will get for ch5 asyn-inverter in ccm compensation are as follows : z r2, the voltage divider resistor in between fb and v ref . z c f , feedforward capacitor in parallel with r1. z r c , compensation resistor on comp pin. z c c , compensation capacitor in series with r c and connect to ground z c p , connect in between comp pin and ground. (can be ignored if c p < 10pf) the major steps for getting above results : 1. 2. select suitable inductor to ensure i out(min.) works in ccm, 3. find rhpz(right hand plan zero) location. 4. set f c (cross over frequency) sufficiently below rhpz. for example: 5. 6. which is duty to v out transfer function. 7. find which is the conjugate double pole from lc filter. 8. 9. find c f by placing its zero on fcdp to cancel another double pole. 10.evaluate c p . c p is for canceling the zero from c out (ceramic output capacitor). = = = = ? = 125k (-8) - 0 0 - 1 x 1m r2 then (-8)v v and 1m r1 if . v v v - v x r1 r2 out out fb fb ref osc out(min.) in f x i x 2 d) - (1 x v l < ) abs(v v ) abs(v cycle duty d , i v r where , l 2 d d) - (1 r ) rhpz(boost out in out out(max) out load 2 load + = = = = lower or 6 rhpz f c = . i ) abs(v r where , c x r x 2 2 f : pole load the find out(max.) out load out load lp = = , d) - (1 v g where , g x gm x v f f r get 2 in doc doc p lp c c = = out out in out abs(v ) d = duty cycle = v v +abs(v ) , (lc) x 2 d - 1 f 2 cdp = pole. double the of one cancel to r x f x 2 1 c c cdp c = 10pf. c if ignore be can c . r r x c c p p c esr out p < = . r1 f 2 1 c cdp f = pcb layout considerations z the feedback netwok should be very close to the fb pin. z the compensation network should be very close to the comp pin and avoid through via. z for ch3 current sense, cs should be close to the drain site of external nmos. z keep high current path as short as possible.
rt9911 32 ds9911-05 april 2011 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com outline dimension dimensions in millimeters dimensions in inches symbol min max min max a 0.800 1.000 0.031 0.039 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 d 5.950 6.050 0.234 0.238 d2 4.000 4.750 0.157 0.187 e 5.950 6.050 0.234 0.238 e2 4.000 4.750 0.157 0.187 e 0.500 0.020 l 0.350 0.450 0.014 0.018 v-type 40l qfn 6x6 package d e d2 e2 l b a a1 a3 e 1 see detail a note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options 1 1 2 2

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